#ifndef REG_SYSC_CPU_TYPE_H_
#define REG_SYSC_CPU_TYPE_H_
#include <stdint.h>

typedef struct
{
    volatile uint32_t CPU_SYSC;
    volatile uint32_t GATE_SYS;
    volatile uint32_t SYS_TICK_CALIB;
    volatile uint32_t RESERVED0[1];
    volatile uint32_t PD_CPU_CLKG;
    volatile uint32_t PD_CPU_SRST;
}reg_sysc_cpu_t;

enum SYSC_CPU_REG_CPU_SYSC_FIELD
{
    SYSC_CPU_LCD_I8080_MD_MASK = (int)0x1,
    SYSC_CPU_LCD_I8080_MD_POS = 0,
    SYSC_CPU_CACHE_MEMTST_MASK = (int)0x10,
    SYSC_CPU_CACHE_MEMTST_POS = 4,
    SYSC_CPU_WDT_DBG_MASK = (int)0x100,
    SYSC_CPU_WDT_DBG_POS = 8,
    SYSC_CPU_WWDT_DBG_MASK = (int)0x1000,
    SYSC_CPU_WWDT_DBG_POS = 12,
};

enum SYSC_CPU_REG_GATE_SYS_FIELD
{
    SYSC_CPU_GATE_SYS_EN_MASK = (int)0x1,
    SYSC_CPU_GATE_SYS_EN_POS = 0,
};

enum SYSC_CPU_REG_SYS_TICK_CALIB_FIELD
{
    SYSC_CPU_CPU_ST_CALIB_MASK = (int)0x3ffffff,
    SYSC_CPU_CPU_ST_CALIB_POS = 0,
};

enum SYSC_CPU_REG_PD_CPU_CLKG_FIELD
{
    SYSC_CPU_CLKG_SET_DMAC_MASK = (int)0x1,
    SYSC_CPU_CLKG_SET_DMAC_POS = 0,
    SYSC_CPU_CLKG_CLR_DMAC_MASK = (int)0x2,
    SYSC_CPU_CLKG_CLR_DMAC_POS = 1,
    SYSC_CPU_CLKG_SET_CACHE_MASK = (int)0x4,
    SYSC_CPU_CLKG_SET_CACHE_POS = 2,
    SYSC_CPU_CLKG_CLR_CACHE_MASK = (int)0x8,
    SYSC_CPU_CLKG_CLR_CACHE_POS = 3,
    SYSC_CPU_CLKG_SET_LSQSPI0_MASK = (int)0x10,
    SYSC_CPU_CLKG_SET_LSQSPI0_POS = 4,
    SYSC_CPU_CLKG_CLR_LSQSPI0_MASK = (int)0x20,
    SYSC_CPU_CLKG_CLR_LSQSPI0_POS = 5,
    SYSC_CPU_CLKG_SET_LSQSPI1_MASK = (int)0x40,
    SYSC_CPU_CLKG_SET_LSQSPI1_POS = 6,
    SYSC_CPU_CLKG_CLR_LSQSPI1_MASK = (int)0x80,
    SYSC_CPU_CLKG_CLR_LSQSPI1_POS = 7,
    SYSC_CPU_CLKG_SET_LCD_I8080_MASK = (int)0x100,
    SYSC_CPU_CLKG_SET_LCD_I8080_POS = 8,
    SYSC_CPU_CLKG_CLR_LCD_I8080_MASK = (int)0x200,
    SYSC_CPU_CLKG_CLR_LCD_I8080_POS = 9,
};

enum SYSC_CPU_REG_PD_CPU_SRST_FIELD
{
    SYSC_CPU_SRST_SET_DMAC_N_MASK = (int)0x1,
    SYSC_CPU_SRST_SET_DMAC_N_POS = 0,
    SYSC_CPU_SRST_CLR_DMAC_N_MASK = (int)0x2,
    SYSC_CPU_SRST_CLR_DMAC_N_POS = 1,
    SYSC_CPU_SRST_SET_CACHE_N_MASK = (int)0x4,
    SYSC_CPU_SRST_SET_CACHE_N_POS = 2,
    SYSC_CPU_SRST_CLR_CACHE_N_MASK = (int)0x8,
    SYSC_CPU_SRST_CLR_CACHE_N_POS = 3,
    SYSC_CPU_SRST_SET_LSQSPI0_N_MASK = (int)0x10,
    SYSC_CPU_SRST_SET_LSQSPI0_N_POS = 4,
    SYSC_CPU_SRST_CLR_LSQSPI0_N_MASK = (int)0x20,
    SYSC_CPU_SRST_CLR_LSQSPI0_N_POS = 5,
    SYSC_CPU_SRST_SET_LSQSPI1_N_MASK = (int)0x40,
    SYSC_CPU_SRST_SET_LSQSPI1_N_POS = 6,
    SYSC_CPU_SRST_CLR_LSQSPI1_N_MASK = (int)0x80,
    SYSC_CPU_SRST_CLR_LSQSPI1_N_POS = 7,
    SYSC_CPU_SRST_SET_LCD_I8080_N_MASK = (int)0x100,
    SYSC_CPU_SRST_SET_LCD_I8080_N_POS = 8,
    SYSC_CPU_SRST_CLR_LCD_I8080_N_MASK = (int)0x200,
    SYSC_CPU_SRST_CLR_LCD_I8080_N_POS = 9,
};

#endif

